The analog-to-digital converter (ADC) is an important component in many electrical sensor, control and communications systems. Such systems often require high converter resolution and high speed for best operation.
In the past, high speed ADCs used parallel or "Flash" architectures but were limited in precision by component matching errors inherent in the fabrication process. Other known architectures such as Successive Approximation Register (SAR) and Cascade are all limited in their precision by analog component errors, either because of mismatch or because of noise and nonlinearity. The component errors determine the highest possible resolution attainable with these architectures. High speed ADCs have greater noise, increased nonlinearity, and increased mismatch with respect to lower speed ADCs as a result of the increased bandwidth of the circuits employed.
Another analog-to-digital conversion technique known as sigma-delta (.SIGMA..DELTA.) conversion has been developed with a view to improving conversion accuracy with reduced sensitivity to component mismatch errors. Sigma-Delta analog-to-digital converters use quantizers within a loop, and also include noise shaping filters formed by the loop. Sigma-Delta analog-to-digital converters reduce quantizer noise, and improve the signal-to-noise (SNR) performance. The bandwidth of the noise shaping filter is a fraction of sampling rate employed in the structure. FIG. 1 is a simplified block diagram of a prior-art .SIGMA..DELTA. analog-to-digital converter. In FIG. 1, the analog input signal x(t) is applied over a conductor or signal path 100 to an input port 200 of a sigma-delta modulator 102, which receives a sampling clock by way of an input path 104. The minimum required sampling frequency is ideally at least twice the highest frequency component of the analog input signal, in accordance with the Nyquist sampling criterion. The ratio of the .SIGMA..DELTA. sampling frequency established by the clock signal on path 104 to the Nyquist minimum required sampling frequency is termed the "oversampling" ratio. Conventional quantization noise analysis indicates that the spectral density of the quantization noise can be approximated by white noise. Therefore, quantization noise is conventionally viewed as being constant from DC to one-half the sampling frequency. The spectral density is determined by the total noise power divided by half the sampling frequency. Taking this view, it follows that as the oversampling ratio increases, the amount of noise in a given bandwidth decreases. Therefore, the maximum resolution (the number of output bits) of the converter can be increased, according to conventional analysis, by increasing the oversampling ratio as much as possible to reduce quantization noise.
Sigma-delta modulator 102 of FIG. 1 converts the analog input signal into a low resolution but very high speed digital signal, which appears on data path 106. This low resolution, high speed signal is termed a pulse density modulated signal (PDM) for single-bit digital output streams or an amplitude density modulated signal (ADM) for multiple-bit digital output streams. The analog input signal modulates the density of states of the PDM or ADM output of modulator 102 so that a digital decimation filter, such as 108 of FIG. 1, reconstructs the analog input signal in digital form on output data path 110. Filter 108 of FIG. 1 includes the cascade of a low-pass or bandpass filter 109 and a decimator 113. The action of filter 108 on the pulse density modulated signal suppresses quantizer noise outside the bandwidth of modulator 102. Furthermore, the filtered output signal is decimated to a lower sample rate, as known, by selection of every Nth sample. The PDM or ADM signals contain many states over a time period corresponding to an analog input cycle at a frequency near the upper edge of the modulator or signal passband, which means that the sample rate is much higher than the highest frequency of the analog input signal. In simple quantization without the use of quantizer noise shaping, one form of which is sigma-delta processing, the quantization error is uniformly distributed with frequency in a frequency range between zero Hz (D.C.) to one-half the sample rate of the quantizer. The quantization error or noise is improved over that of a simple quantizer within the passband when using Sigma-Delta processing. The quantization noise within the bandwidth of a Sigma-Delta modulator is reduced by modulation of the density of quantizer states. By comparison with a simple quantizer, the sigma-delta processing makes better use of the multiple PDM or ADM samples available from the modulator for each output sample produced by the decimation filter. The better use is accomplished by shaping the quantization noise spectrum so that it is reduced within the same frequency band as the input signal.
The conversion which takes place in decimation filter 108 of FIG. 1 to produce the reconstructed digital output reduces the sampling frequency from that of the sampling clock frequency employed by the ADC to a lower rate, often near the Nyquist sampling rate with respect to the input signal bandwidth. Such filters are well known in the art.
FIG. 2a illustrates details of modulator 102 of FIG. 1. Elements of FIG. 2a corresponding to those of FIG. 1 are designated by like reference numerals. In FIG. 2a, analog signal applied over conductor 100 is applied to an input port 200 of modulator 102, and is sampled by a switch arrangement represented by a mechanical switch symbol 201. The sampled analog signal is applied to the noninverting (+) input port of a summing (.SIGMA.) circuit 202, which also receives at its inverting (-) input port an analog replica of the PDM output signal of the modulator. Summing circuit 202 takes the difference between the actual sampled input signal and the analog replica, produces a difference or error signal representing the deviation of the PDM output from the actual sampled analog input signal, and applies the resulting difference signal over a path 203 to an accumulating amplifier circuit or integrating amplifier circuit designated 204, which produces a transfer function G(Z)=z.sup.-1 /1-z.sup.1. Details of one embodiment of accumulating amplifier 204 appear below in conjunction with FIGS. 2b and 2c. The signal filtered by filter 204 of FIG. 2a is applied over a path 208 to an analog-to-digital converter (ADC) block 210. A sample output 209 in FIG. 2a allows examination of the output of filter 204. ADC block 210 also receives sampling clock signals from signal path or conductor 104 at its input port 212. Analog-to-digital converter 210 generates the pulse density modulated signal on output conductor 106, and also provides the PDM signal by a path 216 to a digital-to-analog converter (DAC) 218, which generates the replica of the analog input signal on conductor 206 for application to summing circuit 202. Within ADC block 210, the effect of quantization noise may be represented by a summing circuit, illustrated in dashed lines as 211, which receives the input signal over input line 208, and sums it with a quantizing noise signal applied to a second noninverting input port 213.
FIG. 2b is a simplified block diagram representing the function of a typical prior-art accumulator or integrator 204 which may be used in the arrangement of FIG. 2a. Elements of FIG. 2b corresponding to those of FIG. 2a are designated by like reference numerals. In FIG. 2b, the error signal from summing circuit 202 of FIG. 2a is applied over path 203 to a noninverting input port of a further summing circuit 220, where it is summed with a previously accumulated signal fed to a second noninverting input port over a feedback path 224. The previously accumulated signal is updated by addition of the current error signal to produce a new, updated accumulated value. The new, updated accumulated value is applied to a delay element illustrated as a block 222, which delays the accumulated sum, and makes it available after the delay on output signal path 208 and on feedback path 224. Ordinarily, the duration of the delay represented by block 222 is selected to be equal to one sampling clock interval, designated Z.sup.-1.
FIG. 2c illustrates a more detailed embodiment of the forward signal path of the arrangement of FIG. 2b. In FIG. 2c, a first single pole, double throw switch designated generally as 230 includes a movable common member 230a, which switches or toggles between contact terminals 230b and 230c in response to a two-phase clock signal (not illustrated), and a further SPDT switch 234 has movable member 234a toggling between terminals 234b and 234c. The illustrated position of movable members is that occurring during phase 1 (.phi..sub.1) of the clock signal. Also in FIG. 2c, a capacitor 232 is connected between movable switch members 230a and 234a. An operational amplifier (op amp) 236 has its inverting (-) input terminal coupled to switch terminal 234c. Switch terminal 234b and the noninverting (+) input of op amp 236 are grounded. An integrating capacitor 238 is coupled in a Miller feedback manner between the output terminal of op amp 236 and its inverting input port. The output signal is generated on output signal path 208. In FIG. 2c, input switch 230 has its first input terminal 230b connected to a voltage source designated 240, representing the input signal, the magnitude of which is V.sub.i (n-1), and switch terminal 230c is connected to a source 242, of magnitude V.sub.D/A (n-1). Voltage source 242 represents the signal fed back over path 224 of FIG. 2b.
Capacitor 232 of FIG. 2c is charged so that the voltage V.sub.1 stored across its terminals is equal to -V.sub.i (n-1), which is the negative of the input signal. This occurs during .PHI..sub.1, when switch member 230a is connected to terminal 230b, and switch member 234a is connected to terminal 234b. During .PHI..sub.2, switch member 230a is connected to terminal 230c and switch member 234a is connected to 234c. Terminal 230c is connected to the D/A feedback voltage V.sub.D/A (n-1) as shown in FIG. 2C.
In operation of the arrangement of FIG. 2a, the digitized intermediate output PDM or ADM signal, designated y(n), is fed back by means of conductor or data path 216, digital-to-analog converter 218 and conductor or data path 206 to the inverting input of summing circuit 202 to thereby close a feedback loop. Unless the intermediate output signal y(n) is identical to sampled analog input signal x(n), a non-zero error signal is developed by summing circuit 202. This error signal flows through the forward path of the loop to correct the output. The digital intermediate output signal y(n) is both discretely sampled in time and discretely valued in amplitude. Output signal y(n) takes the form of a time series of M-bit data words, where each word represents a digital signal sample. In the case of a pulse density modulated signal, M is unity or one. The operation of the feedback loop causes the discrete amplitude values of these samples to vary with time about the value of the slowly varying analog input signal, with the amplitude of this variation constituting "shaped" quantization noise. The shaped quantization noise differs from the quantization noise added by ADC circuit 210 in FIG. 2a in that its power spectral density is not constant over frequency. Typically, analog-to-digital converter 210 and digital-to-analog converter 218 are coarse converters, and may even be single-bit converters, as mentioned above. Thus, considerable quantization noise may be introduced by analog-to-digital converter 210. It should be noted that unlike analog-to-digital converter 210, digital-to-analog converter 218 introduces no quantization noise into the feedback signal. This fact results from the definition of quantization noise as the error produced by the rounding or truncating of a continuously valued sample to that of a discrete valued sample. Digital-to-analog converter (DAC) 218 rounds or truncates its input, which has been previously rounded or truncated by ADC 210 in an identical fashion. As a result, no quantization error is introduced into the fed-back analog signal reconstructed from the digital output signal from path 216. DAC 218 may, however, add nonquantization error terms such as thermal noise, flicker noise and harmonic distortion.
FIG. 3a illustrates a plot 310 of the signal transfer function or gain, in dB versus frequency f, of the forward transfer function of the circuit of FIG. 2a. The forward transfer function of the circuit of FIG. 2a is described by its Z-transform H.sub.x (Z)=Y(Z)/X(Z), and by the substitution Z=e.sup.-j2.pi.f/fe, which is used to obtain the frequency transfer function H.sub.x (f), where fe is the sample frequency of the sampling clock driving modulator 102 of FIG. 1. The magnitude squared of the transfer function H.sub.x (f) of FIG. 3a is defined between input conductor 200 and data output 106 of FIGS. 1 and 2a. The gain of Hx(f) represented by plot 310 for signal components up to the maximum signal frequency f.sub.b is approximately unity or 1 (0 dB). Frequency f.sub.b represents the bandwidth of the input analog signal, which in this case is also its highest frequency.
FIG. 3b illustrates a plot 312 of the forward noise transfer function or gain, in dB versus frequency f, of the circuit of FIG. 2a. The quantization noise e(n), and all other error terms added in ADC 210 of FIG. 2a, and which appear on signal paths 106 and 216, may be viewed as entering ADC 210 of FIG. 2a at an input port 213. These additional noise terms are effectively applied to a virtual summing circuit 211, which adds the noise terms to the signal. A forward noise transfer function exists between input port 213 and output port 106, and is defined as He(Z)=Y(Z)/E(Z), where E(Z) is the Z-transform of e(n). To obtain the frequency forward noise transfer function from the Z-transform forward noise transfer function He(Z), by the same substitution Z=e.sup.-j2.pi.f/fe mentioned above. Transfer functions Hx(f) of FIG. 3a and He(f) of FIG. 3b differ from each other as a consequence of e(n) entering the circuit of FIG. 2a at a different location from x(n). The gain of H.sub.e (f) as represented by plot 312 of FIG. 3b is smaller than unity for noise components up to a frequency f.sub.c, and therefore has negative gain in dB. The noise is attenuated or reduced by a larger amount from zero Hz to frequency f.sub.b. The negative gain (or attenuation) of noise with respect to the signal between zero Hz and f.sub.b increases the signal-to-quantizer-noise ratio (SNR) at the output of the analog-to-digital converter of FIG. 1. Noise gain 312 of He(f) of FIG. 3b increases from its level at f.sub.b toward 0 dB at a cutoff frequency f.sub.c where f.sub.c &gt;f.sub.b and f.sub.c &lt;f.sub.e /2. Noise 312 of FIG. 3b at frequencies greater than f.sub.c and less than f.sub.e /2 (half he sample rate employed in ADC 210 of FIG. 2a) rises to a level greater than 0 dB. The amount by which the noise gain exceeds zero dB is dependent on the pole and zero locations of G(Z).
The frequency response of decimation lowpass filter 108 of FIG. 1 is illustrated by plot 314 of FIG. 3c. Between zero Hz and f.sub.b, this filter passes all components with an average gain of zero dB. Above frequency f.sub.b, the gain gradually decreases (signal attenuates) toward a floor, and the gain remains near the floor up to f.sub.e /2. The attenuation at frequencies above f.sub.b suppresses the quantization noise components. The amount of attenuation required to improve the resolution of the analog-to-digital converter of FIG. 1 is determined by the relative amounts of quantizer noise lying between zero Hz and f.sub.b, and between f.sub.b and f.sub.e /2. Decimation filter 108 of FIG. 1 will exhibit quantizer noise spectrum levels between f.sub.b and f.sub.e /2 that are lower than the levels between zero Hz and f.sub.b.
FIG. 3d represents, as a line spectrum 316, a noise-free analog input signal lying between zero Hz and f.sub.b. If noise is present in the input signal, a conventional noise spectrum would be associated with the line spectrum. The analog signal input may encompass a range of spectral components between zero Hz and f.sub.b.
FIG. 3e shows as a plot 318 the power spectrum of noise input signal e(n) to ADC 210 of FIG. 2a. As illustrated, the noise signal has a constant density N.sub.e. The noise level at any sample rate is determined by the total ADC noise divided by one half the sample rate.
The spectra of output signal y(n) on output data path 106 of FIG. 2a is represented by plots 320 and 322 of FIG. 3f. The spectral density of plot 320 of FIG. 3f represents the product of noise power spectrum 318 of FIG. 3e multiplied by noise transfer function 312 of FIG. 3b. Plot 322 of FIG. 3f represents signal spectrum 316 of FIG. 3d multiplied by signal transfer function 310 of FIG. 3a. The spectrum represented by plots 320 and 322 of FIG. 3f is modified by lowpass or bandpass filter 109 of decimation filter 108 of FIG. 1 with the transfer function represented by plot 314 of FIG. 3c, to produce spectra illustrated as 416 and 420, respectively, of FIG. 4a. The signal represented by spectra 416 and 420 of FIG. 4a appear on signal path 111 of FIG. 1. In FIG. 4a, the filtered signal spectrum is substantially unattenuated relative to that of plot 322 of FIG. 3f, while the noise components represented by plot 420 are substantially attenuated by comparison with noise components represented by plot 320 of FIG. 3f over the entire band up to f.sub.e /2.
In FIG. 4b, a repeated signal line spectrum, some of which lines are designated 422, extends (in principle) to infinity. A plot 424 of a repeated noise spectrum also extends to infinity. Spectra 422 and 424 represent the output of decimation filter 108 on path 110 of the analog-to-digital conversion system of FIG. 1, obtained by downsampling the filtered signal corresponding to the spectrum of FIG. 4a to a lower rate, typically 2 f.sub.b. Spectra 422 and 424 are at high precision and at reduced sample rate relative to the interpolated output of low-pass filter 109 of FIG. 1. The reduced sample rate or decimation is achieved by forming a data stream representing interpolated samples selected in increments of r.sub.o =f.sub.e /f.sub.s, where r.sub.o is most commonly an integer valued oversampling ratio. The reduced noise components between f.sub.b and f.sub.e /2 are aliased with the components between zero Hz and f.sub.b of this spectrum as a result of decimation. The total signal-to-noise ratio SNR is the ratio of the total signal power represented by plot 422 to the total noise power represented by plot 424. The SNR determined in this fashion is improved by comparison with that of signal 316 of FIG. 3d and noise 318 of FIG. 3e.
The ADM total output y(n) at the output of prior art modulator 106 of FIG. 1, including signal and noise components, is given by its Z-transform EQU Y(Z)=H.sub.x (Z)X(Z)+H.sub.e (Z)E(Z) (1)
Y(z) is filtered by Digital Decimation Filter 108 of FIG. 1. The forward transfer function of Digital Decimation Filter 108, represented by H.sub.D (Z), is a digital lowpass filter function with digital filter arithmetic (rounding and truncation) noise which is desirably smaller than the attenuated noise represented by plot 424 of FIG. 4b, so as not to increase the attenuated noise relative to that obtained with an ideal decimation filter. This condition can be satisfied, in the prior art, by a finite-impulse-response (FIR) filter which has, typically, between 50 and 150 tap weights or coefficients, each of which weights is of finite precision, truncated to the desired output resolution measured in bits. The FIR filter multiplies input ADM signal samples by the coefficients to create products, which are summed to produce a filtered result. The sum of products is carried out without additional truncation. The final output is then truncated to the desired resolution in bits, plus two additional bits.. The filter output with improved resolution u(n) is given by its Z-transform ##EQU1## In the sampled time domain u(n)=x.sub.o (n)+.epsilon..sub.o (n) where x.sub.o (n) is the output signal and .epsilon..sub.o (n) is the output noise, so that u(n) represents the signal on path 111 of FIG. 1. The magnitudes of x.sub.o (n) and x(n) are approximately equal, while the magnitude of e.sub.o (n) is much smaller than the magnitude of e(n). Therefore, the SNR of the output is increased with respect to the SNR of the input signal and input ADC noise. The reduced sample rate output w(n) of analog-to-digital converter of FIG. 1 on path 110 is given by ##EQU2## and is implemented by decimator 113 of FIG. 1. For example, fe=100 Mhz, f.sub.b =500 KHz leads to the selection of one sample out of every 100 samples in a regular periodic fashion.
An integrator or accumulating amplifier 204 of FIG. 2a, with transfer function G(z), is explicitly described by ##EQU3##
G(z) as set forth in equation (4) defines a pole at .omega.=0 and .vertline.z.vertline.=1, delayed by a unit sample. The signal and noise forward transfer functions H.sub.x (Z) and H.sub.e (Z), respectively, are given by EQU H.sub.x (z)=z.sup.-1 H.sub.e (z)=(1-z.sup.-1)z.sup.-1 ( 5)
and therefore the magnitudes of the signal and noise transfer functions as a function of frequency are given by the substitution z=e 2.pi.f/f.sub.e, and results in ##EQU4## Hence, the circuit of FIG. 2a, using the accumulator configuration of FIG. 2b, yields a signal and noise response determined by a delay applied to the signal, together with a null (a zero) applied to the noise at zero Hz (DC).
Structures based on principles similar to those of FIGS. 2a and 2b have been described in the article "A Higher Order Topology for Interpolative Modulators for Oversampling A/D Converters", by Chao et al., published at pp. 309-318 of IEEE Transactions on Circuits and Systems, Vol. 37, No. 3, March 1990, in which the single integrator of FIG. 2a is replaced by a multistage cascade of integrators, with a feedback and feedforward network tapped from each stage of the cascade. The use of a multistage cascade of integrators allows a greater selection of the locations for the poles and zeroes of the noise transfer function and the signal transfer function. This increased selection is the result of the feedforward coefficients and feedback coefficients supplying as many adjustment parameters as there are poles and zeroes. The multistage cascade of integrators eliminates the problem of being underdetermined and is said to have the degrees of freedom required to place the poles and zeroes of the noise shaping filter at any location or set of locations on the Z-plane.
FIG. 5 is a simplified block diagram of a prior-art Nth order .SIGMA..DELTA. modulator 500 with a noise shaping filter 504 providing both feedforward and feedback coefficients designated A and B, respectively, as described in the abovementioned Chao et al. article. In FIG. 5, elements corresponding to those of FIGS. 1 and 2a are designated by like reference numerals. The sampled, band-limited analog input signal X(Z) is applied over path 100 to summing circuit 202, which conceptually coacts with a further summing circuit 532 to form a multiple-input summing circuit designated 530. Summing circuit 530 takes the difference between the analog replica of the output signal appearing on signal path 206 and the analog input signal on signal path 100, and adds to the difference signal a signal produced by a further summing circuit 546, to produce an analog error or correction signal which is applied over a signal path 531.sub.0 to loop noise shaping filter 504. Within loop filter 504, the signal on path 531.sub.0 is applied to an integrator 538.sub.1 and to the input port of a weighting multiplier or amplifier (A.sub.0) 540. Weighting amplifier 540.sub.o weights the signal by coefficient or weight A.sub.0 and applies it to a noninverting input port of a summing circuit 544. Integrator 538.sub.1 integrates the signal, or, more properly, accumulates the signal, and applies the accumulated signal over a path 531.sub.1 to an integrator/accumulator 538.sub.2, and to the inputs of weighting amplifiers 540.sub.1 and 542.sub.1 for weighting by weights A.sub.1 and B.sub.1, respectively. The weighted signals are applied from weighting amplifiers 540.sub.1 and 542.sub.1 to noninverting input ports of summing circuit 544 and 546, respectively. Similarly, integrator/accumulator 538.sub.2 accumulates its input signal, and applies the accumulated signal over a signal path 531.sub.2 to a further integrator/accumulator (not illustrated) of a cascade of further integrator/accumulators, and also to input ports of weighting amplifiers 540.sub.2 and 541.sub.2 for multiplication by weights A.sub.2 and B.sub.2, respectively, and the signals so weighted are applied to further noninverting input ports of summing circuits 544 and 546, respectively. The Nth integrator/accumulator 538.sub.N of FIG. 5 accumulates the signal applied thereto, and applies the resulting accumulated signal over a signal path 531.sub.N to inputs of weighting amplifiers 540.sub.N and 542.sub.N, for multiplication by weights A.sub.N and B.sub.N, respectively, and the signals so weighted are applied to the Nth inputs of summing circuits 544 and 546, respectively. The sum signal produced by summing circuit 546 is applied as a feedback signal, which may be either positive or negative, to input port 536 of summing circuit 530. The sum signal produced by summing circuit 544 is the corrected error signal, which is applied to ADC 210 to produce the desired PDM or ADM signal on signal path 106. As in the arrangement of FIG. 2a, DAC 218 produces an analog replica of the PDM signal.
FIG. 6a illustrates the Noise Transfer Function pole and zero plot in the z-plane obtained for arrangement of FIG. 5 with the weights as defined in the above Chao et al. reference. In the Z-plane of FIG. 6a, the unit circle 450 intersects the positive real (Re) axis at zero Hz. An X identifies the location of each of plural poles generated by the structure of FIG. 5, and "Os" mark the locations of zeroes. The desired pole locations are specified by the feedforward coefficients solely with the initial assumption that the feedback coefficients are zero. Modification of the feedback coefficients to place zeroes at their desired locations results in a movement of the pole locations, represented by the dashed arrows, from their desired positions at the tails of the arrows, to their actual positions at the heads of the arrows, which results in an error in the actual pole locations. This effect is small when oversampling ratios are greater than 30, but is significant at lower oversampling ratios. This leads to significant error in the placement of the noise shaping poles for the latter case. This leads to one or more of the following: reduced noise attenuation, excessive amplification of high offset frequency circulated noise and instability. This will limit the useful effective sample rate of the Sigma-Delta A/D system. FIG. 6b shows the equivalent effect in the Signal Transfer Function pole and zero plot on the z-plane for the arrangement of FIG. 5 with the aforementioned design process. The same pole selection error is obtained in this case. The locations of zeroes are determined by the feedforward coefficients for this transfer function and are completely determined by the desired pole locations.
The prior-art multistage modulator arrangement of FIG. 5 suppresses total baseband quantization noise by providing plural poles and zeroes at various locations, and therefore provides more selectability, over a given bandwidth than single-stage modulators.
Two major limitations arise with respect to the cascade-of-integrators structures, such as that of FIG. 5, when applied to the problem of high speed high precision A/D conversion. The first problem relates to the traditional approach of utilizing the integrator as a building block. Integrators are generally implemented as switched capacitor integrators, or accumulating amplifiers, based upon or equivalent to the circuit shown in FIG. 2c. Finite gain bandwidth product, slewing and other linear and nonlinear errors limit the useful rate at which the switched capacitor integrators can be clocked. Typically, this will limit the modulator sample rate to f.sub.e =5 MHZ or less for an operational amplifier gain-bandwidth product of 100 MHz. This limitation is the result of the drive currents needed to charge the sampling and accumulating capacitors of the circuit in FIG. 2c. The accumulator-integrators of the arrangement of FIG. 5, when implemented as switched capacitor circuits, have speeds which are adequate for audio and control circuit applications, but which may be insufficient for applications such as radar signal processing, High Definition TV, and high speed communications systems.
The second problem or limitation relates to the method by which the coefficients of the cascade-of-integrating circuits are obtained. Structures such as that of FIG. 5 have limitations imposed by the setting of coefficients. In such circuits, the signal transfer function H.sub.x (z) and noise transfer function H.sub.e (z) are defined by ##EQU5##
The selection of the weights A.sub.i and B.sub.i for weighting amplifiers 440 and 442 of FIG. 4 via a desired noise shaping filter H.sub.D (z) of the same order is complicated by the presence of various polynomial terms in the above equations. A solution may be obtained by first setting B.sub.i =0 and solving for A.sub.i (s) with a simplified polynomial, by equating like terms between the denominator polynomials of the prototype filter H.sub.D (Z) and the expanded form of H.sub.e (z). After this is done, weights B.sub.i are obtained by equating like terms of the numerator polynomials of H.sub.D (z) and H.sub.e (z). The numerator is composed of an N order pole at DC added to an adjustment polynomial using B.sub.i. The magnitude of the B.sub.i coefficients are proportional to magnitude of the offset frequencies of that pole. For large oversampling ratios in the range r.sub.o &gt;50, the frequencies are related by 2f.sub.b &lt;&lt;f.sub.e, and as a result B.sub.i &lt;&lt;A.sub.i. The described design process results in only approximate settings for the pole locations of the signal and noise shaping transfer functions, which may result in an operable system, but one which is less than optimum.
It is desirable to have the effective sample rate as near as may be to the actual sampling rate. When the cascade-of-integrators structure is designed for small oversampling ratios, in the range r.sub.o &lt;50, the values of the required weights B.sub.i are larger than for r.sub.o &gt;50 since the zeroes are placed over a wider spectral region relative to the modulator sample rate. This results in a large error in the placement of the poles of both transfer functions, and affects both the optimality of the filter design and its stability. Both the SNR improvement and the increase in circulated high pass noise power is degraded. The latter may results in constraints due to the dynamic range of the ADC and DAC used in the modulator loop. Most importantly, however, the increased circulated high-pass noise power affects stability, since the deviation of the poles from their designed locations is not controlled. This deviation tends to result in actual pole locations lying outside the unit circle in the Z-plane, and thereby, tends to result in instability.
The deviation in the placement of the noise shaping filter poles affects the minimum oversampling ratio that can be used and thereby limits the maximum effective decimator output sample rate (f.sub.s =2f.sub.b) for a given implementation of limited speed. Hence, a modulator that is limited by a 100 MHz operational amplifier gain-bandwidth product may be clocked at a rate f.sub.e =5 MHz and its high precision A/D output is limited to a small effective sample rate f.sub.s &lt;100 KHz.
Improved .SIGMA..DELTA. analog-to-digital converters are desired.